mbist_tsinghua课件讲义.pdfVIP

Memory Built-In Self-Test Memory Built-In Self-Test Cheng-Wen Wu 吳誠文 Lab for Reliable Computing Dept. Electrical Engineering National Tsing Hua University Outline Outline • Introduction • ROM BIST • RAM BIST approaches • RAM BIST architectures −Typical MBIST architectures − March-programmable MBIST − Processor-programmable MBIST • BRAINS: a RAM BIST compiler • Conclusions m05bist5.04 Cheng-Wen Wu, NTHU 2 Memory Cores on SOC Memory Cores on SOC • Embedded memories are among the most common cores in SOC • How to test embedded memories? CPU DSP CPU DSP Bus/IO SRAM Bus/IO SRAM ROM ROM DRAM Flash DRAM Flash m05bist5.04 Cheng-Wen Wu, NTHU 3 Embedded Memory Testing Embedded Memory Testing • Memories are one of the most universal cores − In Alpha 21264, cache RAMs represent 2/3 transistors and 1/3 area; in StrongArm SA110, the embedded RAMs occupy 90% area [Bhavsar, ITC-99] − In average SOC, memory cores will represent more than 90% of the chip area by 2010 [ITRS 2000] • Embedded memory testing is increasingly difficult − High bandwidth (speed and I/O data width) − Heterogeneity and plurality − Isolation (accessibility) −AC test, diagnostics, and repair • BIST is considered the best solution m05bist5.04 Cheng-Wen Wu, NTHU