VHDL语言设计的电子时钟.doc

VHDL语言设计的电子时钟 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity is port(inclk,reset,pause,settime,tszhh,set:in std_logic; light:in std_logic; outa,outb,outc:out std_logic_vector(0 to 6); bitout:out std_logic_vector(2 downto 0)); end szz; architecture arth_szz of szz is signal a,b,c,d,e,f,g,h,i,j,h1,h2,m1,m2,f1,f2:std_logic_vector(3 downto 0); signal mda:std_logic_vector(14 downto 0); signal mdb:std_logic_vector(9 downto 0); signal mseg:std_logic_vector(3 downto 0); signal bit:std_logic_vector(2 downto 0); signal fpa,fpb:std_logic; signal fpc:std_logic_vector(0 to 6); signal led:std_logic_vector(24 downto 0); signal outaa,outbb,outcc:std_logic_vector(0 to 6); type tshzh_st is (s0,s1,s2); signal cs,ns:tshzh_st; begin process(light) begin if lightevent and light=1 then if led=20000 then led=(others=0); else led=led+1000; end if; end if; end process; process(inclk) begin if (inclkevent and inclk=1) then if mda=led then mda=mda+1; fpa=1;fpc=(others=1); else if mda=24999 then mda=mda+1; fpa=0;fpc=(others=0); else mda=(others=0); end if; end if; end if; end process; process(fpa,inclk) begin if (fpaevent and fpa=1) then if mdb=9 then mdb=(others=0); fpb=not fpb; else mdb=mdb+1; end if; end if; end process; process(fpb,inclk) begin if (fpbevent and fpb=1) then if pause=0 then if a=9 then a=(others=0); if b=9 then b=(others=0); if settime=0 then if c=9 then c=(others=0); if d=5 then d=(others=0); if e=9 then e=(others=0); if f=5 then f=(others=0); if g=3 and h=2 then g=0000;h=0000; elsif g=9 then g=(others=0);h=h+1; else g=g+1; end if; else f=f+1; end if; else e=e+1; end