专业英语特点ppt.ppt

* * * * * * * * 2 from sp dp 7 latency fma 1 fma each cycle Dp stalls for 6 cycle. * * * * * * * * * * * * * * * * * * * * * * * * 33 Users Guide for SC on PS3 SCOP3: A Rough Guide to Scientific Computing on the PlayStation 3 See webpage for details Conclusions For the last decade or more, the research investment strategy has been overwhelmingly biased in favor of hardware. This strategy needs to be rebalanced - barriers to progress are increasingly on the software side. Moreover, the return on investment is more favorable to software. Hardware has a half-life measured in years, while software has a half-life measured in decades. High Performance Ecosystem out of balance Hardware, OS, Compilers, Software, Algorithms, Applications No Moore’s Law for software, algorithms and applications 33 Collaborators / Support Alfredo Buttari, UTK Julien Langou, UColorado Julie Langou, UTK Piotr Luszczek, MathWorks Jakub Kurzak, UTK Stan Tomov, UTK * E =c*v^2*f C=capacity; f proposal to v Its on a single chip multiple distinct processing engines multi independent threads of control or program counters Bw discrete chips (on bus) 2GB/s multicore 40 GB/s Latency 60 ns to 3 ns Energy 500 pJ 5 pJ Freq pro v Power proposional to v^2F or v^3 * * * * * * 14 50 tf 88 10 tf 326 5 * * * * * Google: [NYT, June 8, 2006] 2001 (March) 8,000 servers 70M pages/day 2003 100,000 servers 2006 450,000 servers 2010 1,000,000 servers Microsoft 200,000 servers (2006) ? 800,000 servers (2011) Yahoo * * injecting/receiving packets, making routing decisions, buffers to hold packets * Access latency for main memory, even using a modern SDRAM with a CAS latency of 2, will typically be around 9 cycles of the **memory system clock** -- the sum of The latency between the FSB and the chipset (Northbridge) (+/- 1 clockcycle) The latency between the chipset and the DRAM (+/- 1 clockcycle) The RAS to CAS latency (2-3 clocks, chargin