CMOS异步十进制可逆计数器的优化设计.docVIP

PAGE  题目：基于李码的模9递减计数器 CMOS异步十进制可逆计数器的设计与优化 摘 要 详细论述了一个CMOS异步十进制可逆计数器的原理和设计过程，以及仿真结果。本电路的逻辑部分通过软件MAX PLUS 2设计仿真验证正确后，再通过集成电路设计软件CANDENCE在给定的0.5 μm CMOS工艺下，设计出一个高速计数器，具有加法和减法计数的功能，并且可以一键切换，该电路同时具有一键清零的功能。该设计更加简化可逆十进制的逻辑，可以省去更多电路，对于设计更为复杂的集成电路可以直接使用，提供了方便。通过实验得出了NMOS和PMOS的最优化宽长比，当MOS管为最优宽长比时，通过波形分析，得出上升时间为3.5 ns，下降时间为2.5 ns，从而提高了该计数器的计数频率，该计数器的最高频率为166 MHz,并通过优化设计，提高了电路工作的稳定性。附录是异步十进制可逆计数器的SPICE语言的程序。 关键词：异步十进制 可逆计数器 仿真 集成电路 高速计数器 版图 Design and Optimization of CMOS Asynchronous Metric Reversible Counter ABSTRACT The paper describes the principle, design process and simulation results on a CMOS asynchronous decimal reversible counter. In detail, the logical part of circuit is designed and simulated by the software of MAX PLUS2, On the given 0.5 μm micron CMOS process ,design a high-speed counter , which with the function of addition and subtraction ,by using the integrated circuit design software CANDENCE. The layout make the logical of asynchronous metrication reversible counter more simple, so that the work has more advantages. Experimental results show that the NMOS and PMOS optimize the width-length ratio, waveform analysis, come up time 3.5 ns and fall time 2.5 ns, thus increasing the frequency of the counting. The counter frequency of 166 MHz , improve the stabilization of circuit by optimizing the design. The supplement is the SPICE procedure of the Asynchronous Metric Reversible Counter. Keywords: asynchronous metrication reversible counter simulation IC high speed counter territory 目 录  TOC \o 1-3 \h \z \u  HYPERLINK \l _Toc170269834 一 引论  PAGEREF _Toc170269834 \h 1  HYPERLINK \l _Toc170269835 1.1课题的来源及意义  PAGEREF _Toc170269835 \h 1  HYPERLINK \l _Toc170269836 1.2 计数器简介  PAGEREF _Toc170269836 \h 1  HYPERLINK \l _Toc170269837 1.3 CMOS集成电路的性能及特点  PAGEREF _Toc170269837 \h 2  HYPERLINK \l _Toc170269838 二 异步十进制可逆计数器原理与设计  PAGEREF _Toc170269838 \h 4  HYPERLINK \l _Toc170269839 2.1 异步可逆计数器是由异步加法计数器和异步减法计数器的组合