六十进制计数器原程序.docVIP

六十进制计数器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity cnt_60 is port(clk:in std_logic; data_out:out std_logic_vector(7 downto 0); w_out:out std_logic_vector(3 downto 0); datain:in std_logic_vector(3 downto 0); key:in std_logic_vector(4 downto 2) ); end entity cnt_60; architecture one of cnt_60 is signal q :integer range 0 to signal counter: integer range 0 TO 499999; signal cnt1:integer range 0 to signal clr,clk_1hz:std_logic; signal bcd1:std_logic_vector(2 downto 0); signal bcd10:std_logic_vector(3 downto 0); signal bcd1wr,bcd10wr,cin,co:std_logic; signal a0,a1,a2:integer; type table_array is array (0 to 9) of std_logic_vector(0 to 7); signal table:table_array:=1001111100001101010010010001111100001001); begin bcd1wr=not key(4); bcd10wr=not key(3); cin=key(2); process(clk) --此进程作用是分出50MHz方波 begin if clkevent and clk=1 then if cnt1 =then cnt1=0; clk_1hz=not clk_1hz; else cnt1=cnt1+1; end if; end if; end process; process(clk_1Hz,bcd1wr,datain)is --该进程是处理个位计数 begin if(bcd1wr=1)then bcd1=datain(2 downto 0); elsif(clk_1Hzevent and clk_1Hz=1)then if(cin=1)then if(bcd1=5)then bcd1=000; else bcd1=bcd1+1; end if; end if; end if; end process; process(clk_1Hz,bcd10wr,datain)is --该进程是处理十位计数 begin if(bcd10wr=1)then bcd10=datain; elsif(clk_1Hzevent and clk_1Hz=1)then if(cin=1 and bcd1=5)then if(bcd10=9)then bcd10=0000; else bcd10=bcd10+1; end if; end if; end if; end process; process(bcd10,bcd1,cin)is --该进程是处理进位输出的值 begin if(cin=1and bcd1=5 and bcd10=9)then co=1; else co=0; end if; end process; process(bcd1,bcd10,cin)is --该进程是把计算结果送给数码管 begin a0=conv_integer(bcd1); a1=conv_integer(bcd10); a2=conv_integer(co); end process; process(clk)is --该进程是显示部分 begin if clkevent and clk=1 then if(counter99999)then data_out=tabl