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可编辑逻辑器件应用实验报告 浙江万里学院实验报告 课程名称：可编程逻辑器件应用 实验名称：频率计 专业班级：电子091 姓名： 潘益斌 学号： 2009017172 实验题目：对输入信号测量显示频率 二．实验内容： 1.分频：50M分频，分别分频0.5hz和1hz代码如下 library ieee; use ieee.std_logic_1164.all entity div is port(CLOCK_50:in std_logic; bHz:out std_logic; qkHz:out std_logic); end div; architecture hz of div is constant fpb :integer : constant temp:integer : signal aqi :integer range 0 to fpb; constant kfpb :integer :=49999; constant ktemp:integer :=24999; signal kaqi :integer range 0 to fpb; begin process(CLOCK_50) begin if rising_edge(CLOCK_50) then if aqi fpb then aqi = aqi+1; else aqi = 0; end if; end if; end process; process(CLOCK_50) begin if rising_edge(CLOCK_50) then if(aqi = temp) then bHz = 1; else bHz = 0; end if; end if; end process; process(CLOCK_50) begin if rising_edge(CLOCK_50) then if kaqi kfpb then kaqi = kaqi+1; else kaqi = 0; end if; end if; end process; process(CLOCK_50) begin if rising_edge(CLOCK_50) then if(kaqi = ktemp) then qkHz = 1; else qkHz = 0; end if; end if; end process; end; 计数器：对高电平上升沿跳变次数进行计数程序代码如下 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jishu is port(en,clk:in std_logic; data:out std_logic_vector(15 downto 0)); end jishu; architecture aaa of jishu is begin process(en,clk) variable num:std_logic_vector(15 downto 0); begin if en=0 then num:=0000000000000000; elsif en=1 then if clkevent and clk=1 then num:=num+1; data=num; end if; end if; end process; end; 3转化10进制转化为二进制 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity encode is port(bdata:in std_logic_vector(15 downto 0); out1,out2,out3,out4,out5:out std_logic_vector(3 downto 0)); end encode; architecture behave of encode is begin process(bdata) variable tmp,q1,q2,q3,q4:integer; begin tmp:=conv_integer(bdata); q1:=