飞思卡尔XS单片机寄存器.doc

/* Based? on CPU DB MC9S1?2XS25?6_112?, versi?on 3.00.008 (Regis?tersP?rg V2.26) */ /* ** ################################################################### ** Filen?ame : mc9s1?2xs12?8.h ** Proce?ssor : MC9S1?2XS12?8CAL ** FileF?ormat?: V2.26 ** DataS?heet : MC9S1?2XS25?6RMV1? Rev. 1.03 06/2008 ** Compi?ler : CodeW?arrio?r compi?ler ** Date/Time : 23.2.2009, 15:08 ** Abstr?act : ** This heade?r imple?ments? the mappi?ng of I/O devic?es. ** ** (c) Copyr?ight UNIS, a.s. 1997-2009 ** UNIS, a.s. ** Jundr?ovska? 33 ** 624 00 Brno ** Czech? Repub?lic ** http : ce?ssore?xpert?.com ** mail : info@proce?ssore?xpert?.com ** ** CPU Regis?ters Revis?ions: ** - 20.02.2008, V3.00.0: ** - Corre?cted regis?ters addre?ss: ATD0D?IENL 0x02C?C = 0x02C?D ** - Remov?ed bit FSTAT?[RSVD]. ** - REASO?N: Chang?es in the data sheet? (from Rev. 1.00 5/2007 to Rev. 1.01 8/2007). ** - 17.04.2008, V3.00.1: ** - Renam?ed regis?ters TCNTH?/L == TCNTH?i/Lo, TCxH/L == TCxHi?/Lo. ** - REASO?N: Bug-fix (#6048 from the UNIS Issue? Manag?er). ** - 21.05.2008, V3.00.2: ** - Added? regis?ter VREGH?TTR. Added? inter?rupt vecto?r Vhti. ** - REASO?N: Chang?es in the data sheet? (from Rev. 1.01 08/2007 to Rev. 1.02 02/2008). ** - 23.02.2009, V3.00.3: ** - Corre?cted defin?ition? of 16-bit Port AD0 regis?ters to use prope?rly AD0L/AD0H parts?. ** - REASO?N: Bug-fix (#7029 in UNIS Issue? Manag?er). ** ** File-Forma?t-Revis?ions: ** - 19.07.2007, V2.18 : ** - Impro?ved numbe?r of blank?ed lines? insid?e regis?ter struc?tures? ** - 06.08.2007, V2.19 : ** - CPUDB? revis?ions gener?ated ahead? of the file-forma?t revis?ions. ** - 11.09.2007, V2.20 : ** - Added? comme?nt about? initi?aliza?tion of unbon?ded pins. ** - 02.01.2008