可编程逻辑器件vhdl驱动液晶屏幕.docVIP

--在屏幕上显示自己的名字 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity yejingxianshi is ---------实体说明 port( clk,busy,rst:in std_logic; req:out std_logic; dout:out std_logic_vector(7downto 0) ); end yejingxianshi; architecture yejingxianshi_arch of yejingxianshi is type ztstate is (st0,st1,st2,st3,st4,st5,st6,st7,st8,st9,st10,st11,st12,st13,st14,st15,st16,st17,st18); signal state: ztstate; signal n : std_logic_vector(1 downto 0); Begin ------------结构体说明 process(rst,clk) begin if rst=0 then req=0; state=st0; n=00; elsif clkevent and clk = 1 then case state is when st0= if busy = 0 then dout = req=0; state=st1; else state=st0; end if; when st1= req= 1; state=st2; when st2= req= 0; state=st3; when st3= if busy = 0 then dout = --f0 display Chinese model req=0; state=st4; else state=st3; --waiting for signal busy end if; when st4= req= 1; state=st5; when st5= req= 0; state=st6; when st6= if busy=1 then state=st6; else if n=00 then dout = --字符的列坐标 elsif n=01 then dout = elsif n=10 then dout = end if; req = 0; state = st7; end if; when st7= req = 1; state = st8; when st8= req = 0; state = st9; when st9= if busy = 1 then state = st9; else dout =; --行坐标 req = 0; state = st10; end if; when st10= req = 1; state = st11; when st11= req = 0; state = st12; when st12= if busy=1 then state = st12; else if n = 00 then dout = --要显示的名字的区位码，前半部分 elsif n = 01 then dout = elsif n = 10 then dout = end if; req = 0; state = st13; end if;