设计於深次微米cmos制程之功率感知高速类比数位转换积体电路.ppt

. * * * * * * * * * * * * * * * * * * * NTUEE ; Mixed-Signal IC Lab? 陳信樹 台大電機系 陳信樹副教授? National Taiwan University Department of Electrical Engineering 設計於深次微米CMOS製程之功率感知高速類比數位轉換積體電路(Power-Aware High-Speed ADC in Deep Submicron CMOS) 文化大學電機系2011年先進電機電子科技研討會 Outline Motivation High-speed ADC IC design example Digitally-assisted algorithm and architecture Circuit implementation Experimental results Summary * High-Speed ADC Applications Ref [1] * Power-Aware High-Speed ADC Trends Power / Energy Higher resolution requires more energy to achieve. Speed / Bandwidth Resolution and speed are trade-offs. Bottleneck SAR architecture saves power and chip area, but speed is limited by its conversion algorithm. Pipelined architecture achieves high speed by concurrent operations, but OPAs consume considerable power. Digitally assisted ADCs Digitally assisted algorithm alleviates analog circuit requirement; therefore, it takes advantages of advanced processes to trade little digital power to gain the benefits from analog part. * High-Speed ADC Energy vs. SNDR Energy is proportional to resolution (SNDR). FOM (Power / (Sample rate * 2ENOB)) is an indicator to compare different ADC designs. State-of-the-art ADC designs approach 10fJ/c.s. Current world record is 4fJ/c.s. Ref [2] * High-Speed ADC Bandwidth vs. SNDR Bandwidth is inverse proportional to resolution (SNDR). State-of-the-art high-speed high-resolution ADCs are limited by clock jitter around 0.1psrms. Ref [2] * Experiment 1 - Low-Power High-Speed Two-Step ADC Rearrange the timing of two-channel MDACs and apply a self-timing technique to alleviate comparator comparison time and charge injection disturbance Slightly increases CADC accuracy to ease OPA signal swing design Ref [3] Technology 0.13μm Resolution 6-bit Active area 0.16mm2 Supply voltage 1.2V Sample rate 1-GS/s SFDR (Fin@Nq) 40.7dB SNR (Fin@Nq) 33.8dB SNDR (Fin@Nq) 33.7dB Power 49mW FoM 1.24pJ/c.s. * Relieve MSB accuracy requirement by