一种765并行度二相置信传播qc-ldpc译码器的设计与实现-design and implementation of 765 parallel degree two-phase confidence propagation qc - ldpc decoder.docxVIP

一种765并行度二相置信传播qc-ldpc译码器的设计与实现-design and implementation of 765 parallel degree two-phase confidence propagation qc - ldpc decoder.docx

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一种765并行度二相置信传播qc-ldpc译码器的设计与实现-design and implementation of 765 parallel degree two-phase confidence propagation qc - ldpc decoder

哈尔滨工业大学工学硕士学位论文 哈尔滨工业大学工学硕士学位论文 - - II - Abstract Low-density parity-check codes(Low-Density Parity-Check, LDPC) is a kind of linear block error-correcting code defined by sparse matrices.When the code is long enough,the performance of LPDC codes is even better than Turbo codes, which has made it a strong competitor of the fourth-generation communication systems (4G) ,while the encoding schemes based on LDPC codes have been taken into the satellite digital video broadcasting standard DVB-S2 . Recent years, LDPC codes have become one of the hottest topics in the field of error-correcting codes.This paper shows studies on the theory of encoding and decoding of LDPC codes and design and implementation based on FPGA. The main work of the paper is as follows: The definition and construction of the LDPC codes are in the paper, and some common LDPC encoding and decoding algorithms are introduced briefly as well. Based on 765 degree of parallelism,TPMP Offset Min-Sum decoding algorithm, the high speed decoding scheme of QC-LDPC code is ascertained, which gives a very good decoding performance. In the end, based on Stratix IV EP4SGX530 chips of Altera International Limited, the LDPC encoder and the decoder has been implemented. To test the decoder,an encoder is designed to make it a whole test system. (3)In the paper,the performance and the efficiency of the decoder have been greatly improved by modification of the decoder architecture. Firstly, by taking Ping-Pong operation, the decoding of 2 frames of codes has come true, which makes the decoding efficiency double with a little extra resource compared to the traditional methods. Secondly, the utilization rate of FPGA memory reso urce has greatly risen by widen the word of the memory, while the parallel degree has also increased a lot because that Every entry of the memory stores the messages of multiple nodes. At last, nearly a half of the information storage has been saved by the reuse of the memory of variable

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