一种高性能cmos电荷泵锁相环的设计与分析-design and analysis of a high performance cmos charge pump phase locked loop.docxVIP

下载本文档

21
0
约4.44万字
约 82页
2018-06-03 发布于上海
举报
版权申诉

一种高性能cmos电荷泵锁相环的设计与分析-design and analysis of a high performance cmos charge pump phase locked loop.docx

1、原创力文档（book118）网站文档一经付费（服务费），不意味着购买了该文档的版权，仅供个人/单位学习、研究之用，不得用于商业用途，未经授权，严禁复制、发行、汇编、翻译或者网络传播等，侵权必究。。
2、本站所有内容均由合作方或网友上传，本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺！文档内容仅供研究参考，付费前请自行鉴别。如您付费，意味着您自己接受本站规则且自行承担风险，本站不退款、不进行额外附加服务；查看《如何避免下载的几个坑》。如果您已付费下载过本站文档，您可以点击这里二次下载。
3、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等，请点击“版权申诉”（推荐），也可以打举报电话：400-050-0827(电话支持时间：9:00-18:30)。
4、该文档为VIP文档，如果想要下载，成为VIP会员后，下载免费。
5、成为VIP后，下载本文档将扣除1次下载权益。下载后，不支持退款、换文档。如有疑问请联系我们。
6、成为VIP后，您将拥有八大权益，权益包括：VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
7、VIP文档为合作方或网友上传，每下载1次，网站将根据用户上传文档的质量评分、类型等，对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档

一种高性能cmos电荷泵锁相环的设计与分析-design and analysis of a high performance cmos charge pump phase locked loop

AbstractPhase-locked loop (PLL) is a circuit which can synchronize its output signal with an input reference signal in frequency. It’s a fundamental and very important module in analog and mixed-signal integrated circuits. Because of its ability of tracking, acquisition and operating as a narrow-band filter, PLL is widely used in many fields such as astronautics, communication, microprocessor, and so on. One important application of PLL in microprocessor is to provide on-chip clock for the system. It has been a very important module of microprocessor. With the development of integrated circuits and the emergence of SOC (System on Chip) technology, PLL has played so important a role in VLSI circuits that it is worth researching and designing.In this paper, the research and design of a phase-locked loop utilized in RFID Basestation system are described in detail. First of all, the history of phase locked technology and the actuality of researches on it are introduced. Then, beginning with the fundamental principles of a phase-locked loop system, we build the mathematical model. Afterwards, the design process of this project is described in detail, including the analysis and design of the phase/frequency detector, change pump, loop filter and voltage controlled oscillator, as well as the whole circuit system. And then, the system parameters are deducted. At last the circuits are simulated.The main work and innovation include: Design a new PFD circuit which is more effective then the usual one. The whole simulation is based XFAB 0.6um CMOS process. Cadence’ Spectre is used to input the PLL circuit and accomplish the simulation. From the circuit structure and the result of the simulation, we can see the designed CPLL possess the characteristic of low power, high steady. The design can satisfy the RFID Basestation application.Key Words: Phase Locked LoopFrequency and Phase Detector Charge Pump Voltage Controlled Oscillator目录摘要..............................................