一种基于asic的超高速qc-ldpc编译码器设计与实现-design and implementation of an asic - based ultra-high speed qc - ldpc codec.docxVIP

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一种基于asic的超高速qc-ldpc编译码器设计与实现-design and implementation of an asic - based ultra-high speed qc - ldpc codec.docx

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一种基于asic的超高速qc-ldpc编译码器设计与实现-design and implementation of an asic - based ultra-high speed qc - ldpc codec

AbstractLDPC(Low Density Parity-Check codes), was first proposed by Doctor Gallager in 1963. However, it didn’t get people’s attention because of the limit of computation capability. In 1990s, MackKay found LDPC had near-Shannon-limit capability with low encoding and decoding complexity, which brings a great upsurge in the research of LDPC.An ultra high thourghput encoder and decoder chip applied in 100G optical communication is designd in this thesis. The communication system demands the chip should have at least 100 Gbps throughput, 370Mhz maximum operating frequency. Moreover the chip should be still implemented within 15 equivalent milllions gates in Fujisu 40nm technology, which is not easy for the general architecture of QC-LDPC encoder and decoder. Therefore based on the fully understanding about encoding and decoding algorithms of LDPC, the bottlenecks of implementation are pointed out, and a new high throughput architecture is proposed in the thesis.The designed encoder adopts the low complexity parity-check matrix, reorders the encoding datapath to share the adder and multiplier, this can not only increase the hardware utilization but also decrease the resources to a great extent. Additionally, a low complexity shuffle network is propsed to further reduce the resources needed in encoder, compared to traditional Benes network, the new one can save 56 percent resources.According to the fixed point simulation, 15 times iteration are need to achieve 10-6 BERwith the offset 0.1. The decoder adopts partial parallel architecture, and the strategy of localizing irregular wires, regularizing wires between modules is also applied in the decoder to decrease wire overhead. In addition, two frames ping-pang decoding and 8 stages pipeline are adopted to increase hardware utilization and operating frequency.At last, the encoding and decoding system are implemented with the area of 9.1mm2, frequency of 500MHz, 1.3 million gates, and throughput of 135Gbps in Fujisu 40nm te