一种基于bch码的nand flash控制器的分析与设计-analysis and design of nand flash controller based on bch code.docxVIP

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一种基于bch码的nand flash控制器的分析与设计-analysis and design of nand flash controller based on bch code.docx

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一种基于bch码的nand flash控制器的分析与设计-analysis and design of nand flash controller based on bch code

ABSTRACTThe development of architecture and manufacturing process in NAND Flash reduces the memory cost, but it makes the NAND Flash memory more possible to have random errors at the same time, so the error correction algorithm of stronger error correction capability needs to be studied. BCH code is a kind of linear block codes in the finite field correction, and it is able to correct a plurality of random errors in the NAND Flash. This dissertation designed a NAND Flash Controller which is based on BCH code.Firstly, this dissertation introduces the development history of the NAND Flash, the principle of the dislocation generation in the NAND Flash and basic knowledge about BCH error-correcting codes. It also gives in detail the overall architecture of NAND Flash controller, analyses the basic theory of BCH code, and introduces the memory storage structure, external interface and operation timing of the NAND Flash.Secondly, according to the theoretical basis of the BHC code identified in this dissertation, the parameters of the BCH codec module for (8640, 8192, 32) are ascertained. By calculating the BCH code minimum polynomial and polynomial, an 8 bit parallel BCH encoder is designed in this dissertation. Combined with the characteristics of data flow of BCH decoder, this dissertation designs an 8 bit parallel BCH decoder using two levels of assembly line.Then, this dissertation designs the main control module of NAND Flash controller after analyzing its timing constraints. It gives the overall architecture and module controller. Also the dissertation introduces its register group, the design process of the main control logic, and the method to read data, write data, and realize block erase.Finally, the simulation results of the BCH codec and the NAND Flash controller are analyzed. Also, the whole system is verified in the FPGA development board under the clock of 12.5MHz. These analyses show that all functions of this NAND Flash controller meet the design requirem