74ACT11623DW,74ACT11623DWE4,74ACT11623DWG4,74ACT11623NT,74ACT11623NTE4, 规格书,Datasheet 资料.pdfVIP

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74ACT11623DW,74ACT11623DWE4,74ACT11623DWG4,74ACT11623NT,74ACT11623NTE4, 规格书,Datasheet 资料.pdf

74ACT11623DW,74ACT11623DWE4,74ACT11623DWG4,74ACT11623NT,74ACT11623NTE4, 规格书,Datasheet 资料

SCAS059A − D2957, JULY 1987 − REVISED APRIL 1993 • Local Bus-Latch Capability DW OR NT PACKAGE (TOP VIEW) • Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes A1 1 24 GAB PCB Layout A2 2 23 B1 • Center-Pin VCC and GND Configurations A3 3 22 B2 Minimize High-Speed Switching Noise A4 4 21 B3 • EPIC (Enhanced-Performance Implanted GND 5 20 B4 CMOS) 1-m Process GND 6 19 VCC • 500-mA Typical Latch-Up Immunity GND 7 18 VCC GND 8 17 B5 at 125°C A5 9 16 B6 • Package Options Include Plastic Small- A6 10 15 B7 Outline Packages and Standard Plastic A7 11 14 B8 300-mil DIPs A8 12 13 GBA description The 74ACT11623 is designed for asynchronous two-way communication between data buses. The control function implementation allows for maximum flexibility in timing.

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