附录 DE2115引脚表.docVIP

附录 DE2-115实验板引脚配置信息 DE2-115开发板：目标芯片Cyclone IV E EP4CE115F29C7；存储器：64MB x2 SDRAM、2MB SRAM、8MB Flash；通信端口：10/100/1000以太网口 x2、USB 2.0时钟：50MHz x3 振荡器、SMA in/out Altera 串行配置芯片– EPCS64 表 1 拨动开关引脚配置 Signal Name FPGA Pin No. Description I/O Standard SW[0] PIN_AB28 Slide Switch[0] Depending on JP7 SW[1] PIN_AC28 Slide Switch[1] Depending on JP7 SW[2] PIN_AC27 Slide Switch[2] Depending on JP7 SW[3] PIN_AD27 Slide Switch[3] Depending on JP7 SW[4] PIN_AB27 Slide Switch[4] Depending on JP7 SW[5] PIN_AC26 Slide Switch[5] Depending on JP7 SW[6] PIN_AD26 Slide Switch[6] Depending on JP7 SW[7] PIN_A