Decoupled Architecture for DataPrefetching Computer Sciences 数据预取计算机科学的去耦架构.docVIP

Decoupled Architecture for DataPrefetching Computer Sciences 数据预取计算机科学的去耦架构.doc

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Decoupled Architecture for DataPrefetching Computer Sciences 数据预取计算机科学的去耦架构

Decoupled Architecture for Data Prefetching Kai Xu Jichuan Chang xuk@cs.wisc.edu chang@cs.wisc.edu Abstract Although data prefetching is a useful technique in tolerating memory access latency, its implementation introduces overhead and complications to modern processor. As the chip area becomes more plentiful, it is possible having a decoupled coprocessor to unload the burden of the main processor. In this paper, we investigate the issues in designing a Prefetching Co-Processor (PCP), and evaluate this technique using detailed simulation. The results demonstrate that PCP is feasible: it simplifies the main processor’s design and improves performance. Delay tolerance and prefetching scheme integration are also investigated as two important aspects of PCP. Finally we discuss the limitations of PCP, and compare it with other related techniques. Introduction The gap between processor and memory performance has been widening in the past decade. It is thus becoming more important to look at techniques for hiding the latency of memory accesses. Data prefetching is one of the techniques for hiding the access latency. Rather than waiting for a cache miss to initiate a memory fetch, data prefetching anticipates such misses according to memory access patterns and issues a fetch to the memory system in advance of the actual memory reference. However, data prefetching can incur additional overhead for processors, such as access pattern computation, prefetching address computation and information bookkeeping. With ever-increasing numbers of transistors available on a single chip, recent years has seen a growing interest in decoupled architectures, where more than one processor are put on one chip and in charge of handling different functionalities to improve overall performance. The idea of architectural decoupling can also be used in hiding memory latency [2]. In this project, we investigate the issue of reducing the overhead of data prefetching by using a decoupled

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