Testing n the Fourth Dimension在第四密度的测试.pptVIP

ATS00 Testing in the Fourth Dimension Vishwani D. Agrawal Bell Labs, Murray Hill, NJ 07974 USA va@ /cm/cs/who/va The 9th Asian Test Symposium Taipei, December 4, 2000 Present and Future* Cost of Testing in 2000AD 0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/yr Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second Challenges of Testing High-speed tests for transition faults or critical paths are useless unless tests are applied by the ATE at the rated clock speed Too expensive to replace current ATE with high-speed ATE Non-availability of high-speed ATE and lack of compatibility among ATE manufacturers Speed gap between VLSI speed and ATE speed may always exist Noise problems (coupling, mismatch, etc.) in high-speed ATE to DUT interface A Test Problem Methods of Timing Test Indirect Methods Ring oscillator Create long non-functional paths for testing Direct Methods ATE pin multiplexing Reduced voltage testing Variable (slow-fast) clock testing Built-in controllable delay At-speed BIST High-speed clock with slow ATE I/O Ref: Krstic and Cheng, Delay Fault Testing for VLSI Circuits, Kluwer, 1998 Reduced Voltage Test If a circuit passes a slow-speed test at a reduced VDD, then it is expected to work at a higher clock rate with normal VDD (Wagner and McCluskey, ICCAD-85; Hao and McCluskey, ITC-93) Path delay, T(Vdd) = aT0 (1 + kb) + (1 - a)T0 Vdd = supply voltage during test T0 = path delay at rated supply VDD a = delay fraction due to gates on path b = (VDD - Vdd)/VDD k = technology-dependent constant Low voltage critical paths may be different Reduced voltage operation is noise-sensitive A Delay Test (V1,V2) Slow-Clock Test Slow-Clock Test Problems General non-scan circuits: Low path coverage, ATPG too complex Scan circuits: Vector-pair (V1,V2) r