全加器VHDL.docVIP

布尔方程 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fadder_boole is port(ai,bi:in std_logic; ci:in std_logic; si:out std_logic; co:out std_logic ); end fadder_boole; architecture behavior of fadder_boole is begin si=ai xor bi xor ci; co=(ai and bi)or(ai and ci)or(bi and ci); end behavior; with select when library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fadder_withselect is port(ai,bi:in std_logic; ci:in std_logic; si:out std_logic; co:out std_logic ); end fadder_withselect; architecture behavior of fadder_withselect is signal temp:std_logic_vector(2 downto 0); begin temp=ciaibi; with temp select si=0 when 000, 1 when 001, 1 when 010, 0 when 011, 1 when 100, 0 when 101, 0 when 110, 1 when others; with temp select co=0 when 000, 0 when 001, 0 when 010, 1 when 011, 0 when 100, 1 when 101, 1 when 110, 1 when others; end behavior; when else library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fadder_whenelse is port(ai,bi:in std_logic; ci:in std_logic; si:out std_logic; co:out std_logic ); end fadder_whenelse; architecture behavior of fadder_whenelse is signal temp:std_logic_vector(2 downto 0); begin temp=ciaibi; si=0 when temp=000else 1 when temp=001else 1 when temp=010else 0 when temp=011else 1 when temp=100else 0 when temp=101else 0 when temp=110else 1 when temp=111; co=0 when temp=000else 0 when temp=001else 0 when temp=010else 1 when temp=011else 0 when temp=100else 1 when temp=101else 1 when temp=110else 1 when temp=111; end behavior; if then else library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fadder_ifthenelse is port(ai,bi:in std_logic; ci:in std_logic; si:o