等精度数字频计设计.docVIP

摘要 频率检测是电子测量领域的最基本也是最重要的测量参数之一。基于频率测量的重要性，检测频率方法的研究越来越受到重视。本课题的等精度数字频率计设计，采用当今电子设计领域流行的EDA技术，以CPLD为核心，配合ATMEGA16单片机,采用多周期同步即等精度测频原理，实现待测信号频率的等精度频率测量，此外，该系统还可以测量待测信号的周期、脉宽及占空比。 设计中用一块复杂可编程逻辑器件CPLD(Complex Programmable Logic Device)芯片EPM240T100C5N完成各种测试计数功能。在Quartus II平台上，用VHDL语言编程完成CPLD的软件设计、编译、调试、仿真和下载。用ATMEGA16单片机作为系统的主控部件，实现整个电路的测试信号控制、数据运算处理、键盘扫描和控制液晶的显示输出。系统将单片机ATMEGA16的控制灵活性及CPLD芯片的现场可编程性相结合，不但大大缩短了开发研制周期，而且使本系统具有结构紧凑、体积小，可靠性高，测频范围宽、精度高等优点。 本文详细论述了等精度频率计系统各部分硬件电路组成及单片机、CPLD的软件编程设计，对其进行了仿真和硬件验证，达到了较高的测量精度和测量速度。 关键词：等精度测量 频率计 EDA技术 CPLD 单片机 BSTRACT In the field of electronic measurement, the frequency checking is one of most fundamental and critically important measuring methods．Because frequency signal，which is easily transported，has strong resistance to the disturbance and can be measured with high precisionresearch on the method by measuring frequency have more and more significance in the real application． With the help of CPLD and cooperating with the icrocontroller ATMEGA16，the digital frequency design in our program have realized the precision measurement of nalyte signal frequency by adopting the current EDA technique prevailing in the electronic designs and using the principle of multi-period synchrony frequency measurement．Besides，Via selecting buttons，the system can measure the width ofnalyte signals and room-occupying ratio of high level to low level． During the design，a chip EPM in CPLD fulfills various test and count functions．Under the flat of Quartus II，through VHDL language CPLD software design，compilation，debug，simulation and download can be carried out．By use of the ATicrocontroller as the main controlling parts，the AT realizes test signal control，keyboard scan and output display of LD．The system combines the control flexibility of AT with programmable performance of CPLD，so not only can it shorten the period of the development and research，but also has the advantages of compact structure，lie volume，high reliability，wide scope and high pr