时序逻辑电路-网络学堂.PPT

Chapter 7 Sequential Logic Design Principles( 时序逻辑设计原理 );Introduction;Basic Concepts (基本概念);Basic Concepts (基本概念);Basic Concepts (基本概念);Basic Concepts (基本概念);Basic Concepts (基本概念);Basic Concepts (基本概念);思考：能否只用一片1位 全加器进行串行加法？？;暂存;7.1 Bistable Elements (双稳态元件);7.1 Bistable Elements (双稳态元件);Vin1;Metastable Behavior(亚稳态特性);所有的时序电路对亚稳态都是敏感的;7.2 Latches and Flip-Flops(锁存器与触发器);7.2 Latches and Flip-Flops(锁存器与触发器);S-R Latch (S-R锁存器) S-R Latch with Enable (具有使能端的S-R锁存器) D Latch (D锁存器) Edge-Triggered D Flip-Flops (边沿触发式D触发器) Edge-Triggered D Flip-Flops with Enable (具有使能端的边沿触发式D触发器);Scan Flip-Flops (扫描触发器) Master/Slave Flip-Flops (S-R、J-K） (主从式触发器) Edge-Triggered J-K Flip-Flops (边沿触发式J-K触发器) T Flip-Flop (T触发器);S-R Latches (S-R锁存器);Q;Q;Q;S Q R QL;状态图 ;tpw(min);S-R锁存器的动作特点;第7章作业;Draw the Output Waveform of the S-R Latch ;Chapter 7 Sequential Logic Design Principles( 时序逻辑设计原理 );Review of Last Class (内容回顾);时序逻辑电路 输出取决于输入和过去状态 电路特点：有反馈回路、有记忆元件 双稳态元件 ;S - R latch（锁存器）;S-R Latch with Enable(具有使能端的S-R锁存器);0 X X 1 0 0 1 0 1 1 1 0 1 1 1;D Latch (D锁存器);Level-Sensitive D Latch;Level-Sensitive D Latch;特征方程：Qn+1 = D（C=1）;tpw(min);Q;D Latch with CMOS Transmission Gate(利用CMOS传输门的D锁存器);QL;QL;D Q C Q;Q D Q C;Storing One Bit Example Requiring Bit Storage;*;*;First attempt at Bit Storage;Bit Storage Using an SR Latch;Bit Storage Using an SR Latch;*;*;*;*;Problem with SR Latch;Problem with SR Latch;Problem with SR Latch;Problem with SR Latch;Solution: Level-Sensitive SR Latch;Solution: Level-Sensitive SR Latch;Flip-Flops (触发器);Flip-Flops (触发器);D Flip-Flop;D Flip-Flop;D Flip-Flop;*;D Flip-Flops (D触发器);D;D;D;利用触发器作为移位寄存器（图1）;*;Problem with Level-Sensitive D Latch;Problem with Level-Sensitive D Latch;Problem with Level-Sensitive D Latch;Flight-Attendant Call Button Using D Flip-Flop;Flight-Attendant Call Button Using D Flip-Flop;Timing Parameters for a D Flip-Flops (D触发器的定时参数);利用CMOS传输门实现 —— 主从结构;Clock Signal;*;第7章作