vhdl双语教学第十一章.pptVIP

VHDL Simulation Synthesis Balance of Signal Delay Optimize of Late Arrived Signal Multiple ‘IF’ Statement Late Arrived Signal Late Arrived Signal (Improvement) Priority Encoded ‘IF’ For Late Arrived Signals Priority Encoded ‘IF’ For Late Arrived Control Signal Late Arrived Control Signal Late Arrived Control Signal (Improvement) Improved Code Late Arrived Signal in ‘CASE’ Statement (contd.) Improved Code (Schematic) VHDL Code Before Optimize(Case-When Clasue) VHDL Code After Optimize(Case-When Clasue) Delay in ‘CASE’ Statement (Schematic) Delay in ‘CASE’ Statement (Improvement) Delay in ‘CASE’ Statement Improved Code Long Calculation Path Long Calculation Path (Schematic) Improved Code Improved Code (Schematic) Decoder Using Indexing Decoder Using Loop Decoder Using Indexing vs. ‘Loop’ Multiple Inputs XOR Gate XOR Chains (Schematic) XOR Tree XOR Tree (Schematic) Multiplex Chain Multiplex Chain (Schematic) Multiplex Tree Operator in Conditional Expression Schematic Improved Code Improved Code (Schematic) Unintentional Latch Unnecessary Calculation in ‘LOOP’ Coding Style For Synthesis (1) Omit wait for XX ns; Omit (Q =0 after XX ns) Using shifter register instead Coding Style For Synthesis (2) Omit Initial Values variable SUM:INTEGER:=0; Using power on set/reset signal instead Coding Style For Synthesis (3) Do not use variables for constants Use const Coding Style For Synthesis (4) Indenting Your Codes Coding Style For Synthesis (5) Use std_logic 9 value Automatically initialized to an unknown value Easy to perform a board-level simulation Coding Style For Synthesis (6) Do not use buffers Data_in Data_out Cond_1 D Q D Q D Q D Q R S * * ? ? Late Arrived Signal Late Arrived Signal ? ? 所有能选通b的控制信号组合 Escape from previous 2 ‘if’, but should be caught by ‘z=b’ selection End if; A(1) A(2) A(3) A(4) A(5) A(6) z C(1) C(2) C(3) C(4) C(5) A(1) A(2) A(3) A(4) A(5) A(6) z1 C(1) C(2) C(3) C(5) C(4) A(4) z1 z Merge both the C condition an