VHDL数字电路设计教程（巴西)佩德罗尼第六讲顺序代码.pptVIP

* EXIT: 结束整个循环操作 [label:] EXIT [label] [WHEN 条件表达式]； NEXT: 跳出本次循环操作 [label:] NEXT [loop_label] [WHEN 条件表达式]； 例： FOR i IN 0 TO data’range LOOP case data(i) is when ‘0’ =count:=count+1; when others= EXIT; end case; END loop; * 例6.8 逐级进位加法器（vs 并行进位加法器） 功能描述：最为常用的基本功能模块。 输入矢量a和b为8位无符号数，cin为输入的进位位，s为输出的和，cout为输出的进位位； sj= aj XOR bj XOR cj； cj+1 = (aj AND bj) OR (aj AND cj) OR (bj AND cj); 一位全加器 + a0 b0 c0 (cin) s0 c1 + a1 b1 s1 + a7 b7 s7 c2 c7 c8 (cout) + a b cin s cout 8位逐级进位加法器 * 代码的实现方案一：----使用generic语句 library ieee; use ieee.std_logic_1164.all; entity adder is generic (length: integer : =8); port (a, b: IN std_logic_vector (length-1 donwto 0); cin: IN std_logic; s: OUT std_logic_vector (length-1 downto 0); cout: OUT std_logic ); end adder; architecture adder of adder is begin process (a, b, cin) variable carry: std_logic_vector (length downto 0); begin carry(0) : = cin; for i IN 0 TO length-1 LOOP s(i)= a(i) XOR b(i) XOR carry(i); carry(i+1):= (a(i) AND b(i) ) OR (a(i) AND carry(i)) OR (b(i) AND carry(i)); end LOOP; end process; end adder; * 代码的实现方案二： ----不使用generic语句 library ieee; use ieee.std_logic_1164.all; entity adder is port (a, b: IN integer range 0 to 255; c0: IN std_logic; s: OUT integer range 0 to 255; c8: OUT std_logic ); end adder; architecture adder of adder is begin process (a, b, c0) variable temp: integer range 0 to 511; begin if (c0=‘1’) then temp:=1; else temp:=0; end if; temp:=a+b+temp; if (temp255) then c8=‘1’; temp:=temp-256; else c8=‘0’; end if; s=temp; end process; end adder; std_logic_vector类型，不能直接temp：=c0； integer类型，可直接进行算术运算； Temp范围s范围 * 6.