HDL语言介绍.ppt

信号与变量的区别（1） architecture rtl of start is signal count : integer range 0 to 7; begin process(clk) begin if (clkevent and clk=1) then count = count + 1; if(count=0) then carryout = 1; else carryout = 0; end if; end if; end process; end rtl; architecture rtl of start is begin process(clk) variable count : integer range 0 to 7; begin if (clkevent and clk=1) then count := count + 1; if(count=0) then carryout = 1; else carryout = 0