基于vhdl时钟设计说明书.docVIP

12/24小时数字钟设计顶层图 12/24小时数字钟设计顶层图 二、模块和程序 1、计数器25000 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity yourname_cnt25000 is port(clk:in std_logic; clkout:out std_logic); end yourname_cnt25000; architecture bav of yourname_cnt25000 is signal cnt:integer range 0 to 24999; begin process(clk) begin if clkevent and clk=1 then if cnt=24999 then cnt=0; else cnt=cnt+1; end if; if cnt12500 then clkout=1; else clkout=0; end if; end if; end process; end bav; 2、去抖模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity yourname_qudou is port(key_in,clk_1kHz:in std_logic; key_out:out std_logic); end yourname_qudou; architecture behav of yourname_qudou is signal cnt20:integer range 0 to 19; begin process(clk_1kHz,key_in) begin if clk_1kHzevent and clk_1kHz=1 then if cnt20=19 then cnt20=0; key_out=key_in; else cnt20=cnt20+1; end if; end if; end process; end behav; 3、万年历模块 万年历顶层电路图 ①年月日星期模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity yourname_ymdx is port( preset:in std_logic; co:in std_logic; date: out std_logic_vector(7 downto 0); month,year:out std_logic_vector(7 downto 0); xingqi:out std_logic_vector(3 downto 0)); end yourname_ymdx; architecture bav of yourname_ymdx is signal yue:std_logic_vector(7 downto 0):=; signal nian:std_logic_vector(7 downto 0):=; signal ri:std_logic_vector(7 downto 0):=; signal xingqi1:std_logic_vector(3 downto 0):=0010; signal cnt:std_logic_vector(7 downto 0):=; signal qm:integer range 28 to 31; begin process(yue,nian) begin case yue is when =qm=31; when = if (nian(0)=0) and (nian(1)=0) then qm=29; else qm=28; end if; when=qm=31; when=qm=30; when=qm=31; when=qm=30; when