xilinx时序约束培训课本.pdfVIP

Constraints Practical Design for Xilinx!! 该文的版权归Xilinx公司所有！ 由收集整理。 Make EDA serve you! Practical Design for Xilinx, Section 7, 12/29/98 Page 1 When to use Timing Constraints? Constraints add to run time, so don’t use them unless you need to Faster designs need constraining — it depends on the speed grade of the device selected, but in general, any design with a clock speed of 50MHz or less and a reasonable number of logic levels (7 or less), doesn’t need timing constraints — designs over 50MHz should use timing constraints Designs with multiple clock should have timing constraints — if you have a signal clock and are under the 50MHz limit above, you will not need timing constraints - you can always add them later if you need to If you have multi-cycle clock paths, you need constraints — these are paths where you know you have two or more clock cycles for logic to steady- state after an input change Rule of Thumb: run non-timing driven PAR without constraints, unless you are not reaching your timing goals. — add constraints sparingly, DO NOT over constrain your design - it won’t help, and increases can increase your run time dramatically!! Practical Design for Xilinx, Section 7, 12/28/98 Page 2 Why use Design Constraints? Constraints allow you to lock your pins after the board pin out is fixed — Xilinx M1.5i software has automatic pin locking, and uses the constraints file to pass these pin locks to future runs of the design Constraints allow you to give your exact timing requirement to the place and route or fitting software — for many designs, the constraints are not needed for place and route to meet timing - but are an excellent way to get a