数字电子技术(课件)lec21.pptVIP

* Chapter 9 Shift Registers * Used as Parallel In/Parallel Out Register Lecture 21: Various Shift Registers See demo * Chapter 9 Shift Registers * Used As Serial In/Serial Out Shift Register Lecture 21: Various Shift Registers See demo * Chapter 9 Shift Registers * Used As Serial In/Parallel Out Shift Register Lecture 21: Various Shift Registers 7-Bit Serial In/Parallel Out Shift Register Serial in Parallel out mark See demo Initially reset, after 1st cp, what data is in registers? After how many cp, mark 0 is shifted to Q3? * Chapter 9 Shift Registers * Lecture 21: Various Shift Registers Used As Parallel In/Serial Out Shift Register Start signal 7-Bit Parallel In/Serial Out Shift Register Serial out Parallel data Mark bit See demo When mark bit 0 moves to Outputs last data bit * Chapter 9 Shift Registers * Test Your Understanding 2. To serially shift a byte of data into a shift register, there must be a) one clock pulse; b) one load pulse c) eight clock pulses; d) one clock pulse for each 1 in the data. Answer: c) Lecture 21: Various Shift Registers A stage in a shift register consists of a latch; b) a filp-flop; c) a byte of storage; d) four bits of storage. Answer: b) * Chapter 9 Shift Registers * Test Your Understanding Lecture 21: Various Shift Registers 3. To parallel load a byte of data into a shift register with a synchronous load, there must be a) one clock pulse b) eight clock pulses c) one clock pulse for each 1 in the data. d) one clock pulse for each 0 in the data. Answer: a) 4. The group of bitsis serially shifted ( right-most bit first) into an 8-bit parallel output shift register with an initial state of After two clock pulses, the register contains: a) b) c) d) Answer: c) * Chapter 9 Shift Registers * Summary of Lecture 21 Data delay time for n-stage shift register is: td=nTcp Be careful about two types of parallel data loading method: the synchronous and asynchronous