ADDA等一些芯片的verilog程序.doc

/* AD0809 module v1.0 work up to 5M sample = 25us 40khz for normal clk = 2.5M sample = 30us 33khz */ module ad0809( clkin, adclk, eoc, st, ale, datain, oe, dataout ); input clkin; input eoc; input [7:0]datain; output st; output ale; output oe; output adclk; output [7:0]dataout; reg adclk; reg [7:0]dataout; reg st; reg oe; reg ale; //frequence divider for AD parameter Div_adclk = 8d9;//(9+1)*2=20 adclk=2.5M parameter Div_clk_state = 4d4;//(4+1)*2=10 clk_state=5M reg [8:0]div_cnt_ad;//frequence div cnt reg [3:0]div_cnt_state; reg clk_state; always@(negedge clkin)begin if(div_cnt_ad != Div_adclk) div_cnt_ad = div_cnt_ad + 1b1; else begin div_cnt_ad = 0; adclk = ~adclk; end if(div_cnt_state != Div_clk_state) div_cnt_state = div_cnt_state + 1b1; else begin div_cnt_state = 0; clk_state = ~clk_state; end end /*AD convert*/ reg [3:0]state; reg [7:0]delay; initial begin state = 4d0; end always@(negedge clk_state)begin case(state) 4d0:begin //clear all st = 1b0; oe = 1b0; ale = 1b0; delay = 8h00; state = 4d1; end 4d1:begin //ale latch ale = 1b1; state = 4d2; end 4d2:begin //st rasing st = 1b1; state = 4d3; end 4d3:begin //ale falling ale = 1b0; state = 4d4; end 4d4:begin //st falling st = 1b0; state = 4d5; end 4d5:begin//eoc delay after st; 8clock+2us = 26stata_clk delay = delay + 1b1; if(delay == 8d26) state = 4d6; else state = 4d5; end 4d6:begin //test eoc(convete finished); if(eoc) state = 4d7; else state = 4d6; end 4d7:begin //out enable oe = 1b1; state = 4d8; end 4d8:begin //take data dataout = datain; state = 4d9; end 4d9:begin //out unable; return oe = 1b0; state = 4d0; end default: state = 4d0; endcase end endmodule /* clk = 5Mhz T = 0.2us the distance = 0.2