嵌入式系统导论3硬件设计8260.pptx

专题2 MPC8260设计;1、MPC8260简介;双CPU结构 PPC603e演生版 支持150-300MHz主频 独立16K数据和指令 Cache MMU 通用片内处理器测试接口(COP) 高性能(1.68MIPS/MHz,1.90 Dhystone MIPS/MHz) 浮点处理单元(FPU) 内部逻辑和I/O独立供电 G2 Core和CPM具有独立PLLs Core/Bus clock(1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1) CPM/Bus clock(2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1);64-bit data and 32-bit address 60x bus Bus supports multiple master designs Supports single- and four-beat burst transfers 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller Supports data parity or ECC and address parity 32-bit data and 18-bit address local bus Single-master bus, supports external slaves Eight-beat burst transfers 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller ;System interface unit (SIU) Clock synthesizer Reset controller Real-time clock (RTC) register Periodic interrupt timer Hardware bus monitor and software watchdog timer IEEE 1149.1 JTAG test access port ;Twelve-bank memory controller Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-definable peripherals Byte write enables and selectable parity generation 32-bit address decodes with programmable bank size Three user programmable machines, general-purpose chip-select machine, and mode pipeline SDRAM machine Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local) CPU core can be disabled and the device can be used in slave mode to an external core ;Communications processor module (CPM) Embedded 32-bit communications processor (CP) uses a RISC architecture Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller 3 *FCC(Fast communications controllers) 10/100M Ethernet(MII) 155M ATM(Full-duplex,UTOPIA) HDLC-45M 2*MCC(multichannel controllers) Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. 4*TDM ;4*SCC(serial communications controllers) Ethernet/IEEE 802.3 CDMA/CS HDLC/SDLC and HDLC bus Universal asynchronous receiver transmitter (UART) Synchronous UART Binary synchron