SDR SDRAM 控制器白皮书 中英文对照版.pdfVIP

SDR SDRAM 控制器白皮书 中英文对照版 SDR SDRAM 控制器白皮书 中英文对照版 翻译：合肥工业大学 检测技术研究所 彭良清（peng6602@ ） 日期：2004/4/24 原文：/literature/wp/sdr_sdram.pdf Introduction The single data rate (SDR) synchronous dynamic random access memory (SDRAM) controller provides a simplified interface to industry standard SDR SDRAM. The SDR SDRAM Controller is available in either Verilog HDL or VHDL and is optimized for the Altera® APEX™ architecture. The SDR SDRAM Controller supports the following features:  Burst lengths of 1, 2, 4, or 8 data words  CA