毕业论文设计《AS_001基于FPGA的HDB3编译码的建模与实现》.docVIP

PAGE 基于FPGA的HDB3编译码的建模与实现 摘 要 本文以FPGA为硬件平台，基于EDA工具QUARTUSⅡ为软件平台上对HDB3编/译码进行实现。由于在EDA的软件平台QUARTUSⅡ上不能处理双极性的信号，因此对HDB3码的编/译码的实现分为：软件部分和硬件部分。软件部分是基于QUARTUSⅡ的平台上对输入的码元进行编码和译码，通过系统仿真，验证了HDB3码的编译码的正确性；硬件部分采用CD74HC4052双四选一的数模选择器实现单极性到双极性的转换；采用AD790和SE5539实现双极性到单极性的转换。最后，通过仿真，验证了方案的正确性。 关键词：HDB3；建模；VHDL；编/译码；QUARTUSⅡ The Modeling and Realization of the HDB3 Encoding and Decoding Based on FPGA Wu Yingfa (College of Physics Science and Information Engineering,Jishou University,Jishou,Hunan Abstract The HDB3 encoding and decoding are realized based on taking FPGA as hardware platform and taking QUARTUSⅡ，a kind of EDA tool，as the software platform. Because QUARTUSⅡ can not deal with the bipolar of signal，the realization of HDB3’s encoding/decoding function is divided into two parts: software and hardware part. In the software part: the encoding/decoding of HDB3 are realized based on QUARTUSⅡ, and the simulation result that the realization is correct. In the hardware part: the CD74HC4052 are used to realize unipolar /bipolar transformation, at the same time, the AD790 and SE5539 are used to realize bipolar/unipolar transformation. At last, the efficiency of the above method is proved by the simulation results. Key words： HDB3；Modeling；VHDL；Encoding/Decoding；QUARTUSⅡ 目 录 TOC \o 1-3 \u 第一章 绪 论 PAGEREF _Toc138440986 \h 1 第二章 EDA辅助设计工具的介绍 PAGEREF _Toc138440987 \h 3 2.1 FPGA的介绍 PAGEREF _Toc138440988 \h 3 2.1.1 PLD的介绍 PAGEREF _Toc138440989 \h 3 2.1.2 FPGA的系统介绍 PAGEREF _Toc138440990 \h 3 2.2 VHDL语言和QUARTUSⅡ PAGEREF _Toc138440991 \h 4 2.2.1 VHDL语言 PAGEREF _Toc138440992 \h 4 2.2.2 EDA工具QUARTUSⅡ PAGEREF _Toc138440993 \h 5 第三章 HDB3码编码器的建模与实现 PAGEREF _Toc138440994 \h 6 3.1 HDB3码的编码规则 PAGEREF _Toc138440995 \h 6 3.2 基于VHDL的编码器的建模及实现 PAGEREF _Toc138440996 \h 6 3.2.1 编码器的VHDL建模及难点分析 PAGEREF _Toc138440997 \h 7 3.2.2 基于VHDL编码器的实现 PAGEREF _Toc138440998 \h 7 3.3编码中单/双极性转换的实现 PAGEREF _Toc138440999 \h 11 3.3.1单/双极性转换的流程图 PAGEREF _Toc138441000 \h 11 3.3.2单/双极性变换的VHDL实现 PAGEREF