Ansoft高速信号完整性详细教材.ppt

Examples Involving Measured Data With Comparisons to SIwave Add Caparray_1 and _2 decoupling capacitors Place 22xcap (1e-07F,0.2Ohm ,2e-09H) 22xcap (1e-08F, 0.2Ohm, 2e-09H) near the center of board (5500,3600) Caparray_2 Plane Impedance w/ Caparray_1 and Caparray_2 Parallel resonance will occur here Bare Board Caparray_1+_2 Time Domain Power/Ground Bounce Waveform w/ Caparray_1+_2 Ground Bounce has been improved a lot!!! But, still doesnt meet the design goal Add more Caps Caparray_3 Add the caparray_1+_2+_3 Place 22 x cap (1e-07F,0.2Ohm ,2e-09H) 22xcap (1e-08F, 0.2Ohm, 2e-09H) 22xcap (1e-09F, 0.2Ohm, 1e-09H) near the center of board (5500,3600) Caparray_1 vs Caparray_1+_2 vs Caparray_1+_2+_3Impedance Impedance w/ caparray_1+_2+_3 Bare Board Time Domain Power/Ground Bounce Waveform w/ Caparray_1+_2+_3 Almost meet the design goal of Power Bounce. Next Step Export Entire Board’s Full Wave Spice Model. Positions of the Decoupling Capacitors and IC Export Full-Wave-Spice-Model for PCB Plane Port for IC at (4,3) Port for IC at (5,4) Port for IC at (6,4) Port for VRM at (1,1) A litte bit over spec. Need to add more decaps Current sink and Power/Ground Bounce Voltage at IC(4,3) Enhanced Decaps Schematic with Total decaps Add enhanced decap_gp The total Decaps be added in this PCB Decaparray_1+_2+_3+enhanced decap_gp Target !!! IC(4,3) Impedance value for w/wo decap_gp With enhanced decap_gp Without enhanced decap_gp Bingo!!! We meet the PI design goal. Current sink and Power/Ground Bounce Voltage on IC(4,3) Power Integrity Design Flow using Full-Wave field solver (Ansoft SIwave) STEP1 : Resonant modes 1.1 Pre-layout PDS’s power/ground plane structures(Layer stack-up, Materials,Shapes) to make the inherent natural resonant modes (usually first) not occur with the target impedance required band-width or in the higher band. 1.2 Preview the voltage distribution of the resonant mode, avoid to place ICs which draw large currents near the resonant’ voltage peaks/dips