数字电路英文版第七单元.pptVIP

KEY TERMS ABEL Advanced Bollean Expression Language. A software compiler language for PLD programming; a type of hardware description language (HDL). Architecture The internal functional arrangement of the elements that give a device its particular operating characteristics. Array In a PLD, a matrix formed by rows of product-term lines and columns of input lines with a programmable cell at each junction. Buffer A circuit that prevents loading of an input or output. Cell A fused cross point of a row and columnn in a PLD. Complier Software that translates from high-level language that uses words or symbols, such as HDL , into low-level machine language (1s and 0s). Documentation file The information from a computer that documents the final design after the input file has been processed. E2CMOS Electrically earsable CMOS ( EECMOS). The circuit technology used for the reprogrammable cells in GAL. Fuse The programmable element in certain types of PLDs; also called a fusible link. GAL Generic array logic. A PLD with a reprogrammable AND array, a fixed OR array, and programmable output logic macrocells. Input file The information entered in a computer that describes logic design using a PLD programming language such as HDL. Input/Output (I/O) A terminal of a device that can be used as either an input or as an output. OLMC Output logic marcocell. The programmable output logic in a GAL. PAL Programmable array logic. A PLD with a programmable AND array and a fixed OR array. PLA Programmable logic array. A PLD with a programmable AND and OR array. PLD Programmable logic device. Programmer An instrument that programs PLD using a JEDEC file downloaded from a computer running HDL software. Software Computer programs; programs that instruct a computer what to do in order to carry out a given set of tasks. Synthesis The software process of converting a circuit description to a standard JEDEC file for PLD programming. Tristate output buffer A lo