Analysis of Bandwidth–Unit-Vector-Distortion英文版本.pdfVIP

5820 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 12, DECEMBER 2013 Analysis of Bandwidth–Unit-Vector-Distortion Tradeoff in PLL During Abnormal Grid Conditions Abhijit Kulkarni, Student Member, IEEE, and Vinod John, Senior Member, IEEE Abstract—Phase-locked loops (PLLs) are necessary in applica- in [9] and [10] wherein zero-crossing detection is used to make tions which require grid synchronization. Presence of unbalance the system frequency adaptive. In [11] and [12], PLL structures or harmonics in the grid voltage creates errors in the estimated based on enhanced PLLs are explained for better performance. frequency and angle of a PLL. The error in estimated angle has the effect of distorting the unit vectors generated by the PLL. PLL with in-loop lead compensator is proposed in [13]. In this paper, analytical expressions are derived which determine A feature of most of the high-performance PLLs is that the error in the phase angle estimated by a PLL when there they have an equivalent SRF-PLL embedded in them. The is unbalance and harmonics in the grid voltage. By using the high-performance PLLs provide reduced unit vector THD but derived expressions, the total harmonic distortion (THD) and the have higher complexity and might require a high-end digital fundamental phase error of the unit vectors can be determined for a given PLL topology and a given level of unbalance and controller for implementation. It is known that SRF-PLL can distortion in the grid voltage. The accuracy of the results obtained provide better performance [15], [16] at lower bandwidth. How- from the analytical expressions is validated with the simulation