coding_and_synthesis_with_verilog外文部分.pdfVIP

1.0 Verilog Synthesis Methodology Finbarr O’Regan (finbarr@ee.ucd.ie) October 2001 Synthesis is a contraint driven process i.e. the synthesis script needs timing constraints Follow the following methodology for best results 1. Draw a simple block diagram, labelling all signals, widths etc. 2. Draw a timing diagram with as much detail as possible 3. Code the HDL according to the synthesizable templates 4. Do a quick, low effort, compile- just to see if it is synthesizable before simulating. Compare this to the block dia- gram. Look at the inference report: • co