低压差分信号系统的设计-微电子学与固体电子学专业论文.docx

II II Abstract Low Voltage Differential Signaling(LVDS) can be widely used in all kinds of data on demand and high-speed transmission equipment, because it has many good characteristics. This paper based on HJTC 0.18μm mixed digital-analog technology. The main study in this paper includes the following three aspects.The study of LVDS system architecture, circuit design, LVDS system simulation. System architecture mainly concentrates technical parameters, basic principle, architecture and driver circuit, which is dvided into five parts: date reception, DC-balance, PLL, 7-bit serializer, driver circuit. And this paper focuses on bandgap reference circuit, PLL, 7-bit (serializer), driver circuit design. Bandgap reference circuit: first, describing the technical specifications and principle, then, according to the theory and design of the chip to meet the needs of hign-speed bandgap current source, last, giving the circuit simulation process and the outcome. PLL is used to produce 7-phase clock signal, that is, the frequency range of input reference clock is 32.5MHz~112MHz, and 7-phase output clock signal with the same frequency, but the level of signal is 1:7. the circuit design from the beginning of mathematical modeling, using MATLAB simulation gets linear parameters of the system, then according to the parameters to design voltage controlled oscillator (VCO), frequency/ phase detector(PFD), charge pump(CP), a low-pass filter(LPF), divider and regulator, at last, PLL system-level simulation results are given. Data serializer with multi-stage multiplexers main using of the 7-phase clock signal multiplie the signal, with its high-speed, high-precisin features. Driver circuit divided into traditional LVDS divider and pre-emphasis LVDS divider, and pre-emphasis LVDS divider can solve the long-distance signal transmission with the attenuation and interference. After finished the five modular designs, the entire system has been optimized. The simulation results show that t