CMOS电荷泵锁相环的设及相位噪声的研究-微电子学与固体电子学专业毕业论文.docxVIP

Design of a CMOS Charge--Pump PLL and Investigation of the Phase Noise Abstract With the development‘of the integrated circuit technology，the PLL(Phase Locked Loop)obtains more and more attention．CPPLLs(Charge·Pump PLL) become the mainstream and play an important role in VLSI and SoC(System on Chip)because of the merit of smaller phase difference and bigger capture range． This thesis designed a CPPLL which was based on CMOS technology and adopted top·down method．Firstly,the VHDL-AMS behavioral modeling of the close—loop system was desi gned based on the fundamental of CPPLL and the characteri