超大规模集成电路第八次作业2016秋-段成华.docxVIP

Assignment 8 Access relevant reference books or technical data books and give accurate definitions for the following timing parameters: design entity, signal driver, transaction, event, time queue, delta delay, simulation time, simulation cycle, inertial time, transport time. design entity: In VHDL a given logic circuit represented as a design entity. A design entity, in return , consists of two different types of description: the interface description and one or more architectural bodies. The interface description declares the entity and describes its inputs and outputs. signal driver: If a