中科院研究生院课程VLSI测试和可测试性设计.pptVIP

EE141 EE141 Chapter 4 Test Generation Introduction Random Test Generation Theoretical Foundations Deterministic Combinational ATPG Deterministic Sequential ATPG Untestable Fault Identification ATPG for Delay and Bridge Faults Other Topics in Test Generation Concluding Remarks D Algorithm Can handle arbitrary combinational circuits, with internal fanout structures Main idea: always maintain a non-empty D-frontier and try to propagate at least a fault effect to a primary output Initially, all circuit nodes are X, except for the fault cite, where a fault effect (D or D-bar) is placed. D-Frontier