电子科技大学数字逻辑设计及应用数字逻辑.pptxVIP

Describe for time delay;module majority (a,b,c,f); input a,b,c; output f; wire w1,w2,w3; assign #19 w1=~(ab); assign #19 w2=~(bc); assign #19 w3=~(ac); assign #40 f=~(w1w2w3); endmodule;assign #3 a1=a;assign #3 a2=a; assign #3 b1=b;assign #3 b2=b; assign #3 c1=c;assign #3 c2=c; assign #19 w1=~(a1b1); assign #19 w2=~(b2c1); assign #19 w3=~(a2c2); assign #40 f=~(w1w2w3); endmodule;Simulation tool: Modelsim; File/New/Project;Name your project and its path;File/New/Source/Verilog;Save your design：name and path;Compile your design;Design/load Design;Open the simulation window：add wave *;force -r