面向IP核的布图规划与Power+Pad的协同优化.pdfVIP

面向IP 核的布图规划与Power Pad 的协同优化 - II - 万方数据 IP-Core Orinted Foorplanning and Power Pad Co-optimization Abstract As the semiconductor technique enters the deep sub-micron stage, the supply voltage is further reduced, and the metal interconnects occupy more chip area. Besides, the increasing IP cores are integrated into a single chip. All above factors make the IR drop (voltage drop) problem significant at the present stage. Excessive voltage drop may cause the supply voltage can not meet the chip demand, degrade chip performance and even chip fails. The traditional SoC design flow deals with the IR drop problem at the post-layout stage, which may complex the flow and time consuming when the design does not meet the requirements. Therefore, the IR drop problem should be paid more attention and solved effectively in the early physical design cycle. By exploring the SoC design flow and characteristics to optimize the voltage drop and accelerate the CPU time, we propose a heuristic method which can optimize the floorplan and power pads simultaneously. The proposed method is validated by testing the MCNC benchmark circuits.The thesis is mainly composed of the following two sections: 1. Floorplanning has a great impact on the current density distribution of power / ground network. In terms of the voltage drop problem, especially for those high current density IP cores, a