基于JTAG的基带芯片可测试性结构的设计-微电子学与固体物理学专业论文.docxVIP

A A b stra c t T itle : A D F T s tru c tu re d e s ig n fo r b a s e b a n d e h iP b a s e d O n J T A G S ta n d a rd M aj o r: M ic ro e le ctro n ic S o lid P h y s ic s N a m 6 : 5 ig n a tu re : 全 犷 .· S U P G rv IS O r : 5 ig n a tu re : 血里旦{“卜{ A b s tf a C t Wi th th e hi gh sP eed d ev eloP m eni o f V L S I ，int egr at io n rat io o f eh iP an d eireu it eo m P lex ity， th e testin g o f eh iP 15 fac in g to seri o u s eh a llen g e .T h e tr a d itio n a l P h ys ie a l to u c h te stin g w ay 15 e o m P le te ly n o t fu lfi ll th e re q u e st o f e urr en t situ a tio n .U sin g D F T in eh iP d esign Pro eess 15 an in ex orab le tr end . To fu fi ll th e test aP P eal o f eellP ho n e b aseb an d S O C ehi P ，thi s P ap er is do in g a deeP researe h b as ed on JT A G eri teri on an d d esi加 n g a JT A G ini erfac e stru ctur e w h ie h o b e ie s th e IE E E l l 4 9 .l stan d ar d .T h e J l ’A G int e rfa e e stru e tur e d e sign 15 in e lu d e d th e T A P e o n tro ller， re g iste rs，in stru e tio n s an d sc an e e lls . B y d e sign th e T A P e o ni ro lle f， it e an a e h ie v e d th e b a sie e o n tro l o f th e te st m o d e s ，fo r in stan e e ，B Y P A .S S ， ID eod e an d thr ou gh th e in strU etion s lik e E X T E S T，D呵T E S T，S A M P L E to earr y out th e D F T te st lo g ie .Wi th th is fo un d at io n ，e o m b in in g w ith th e e h ar a e teri stie lo ts o f d iffe re ni 几n etion m o du les ini egr at ed in S O C b as eb an d eh iP ，1 en larg ed th e JITA G ini er fac e stru e tUr e to at tai n th e a im to e x P an d th e te st e o n tro l fu n c tio n .I d e sign e d th e e o n tro l lo g ie o f M B IS T，B S ，D E B U 几 即 d u se th em in to th e to P lev el，th en