基于51mx的jtag接口的设计与仿真-软件工程专业论文.docxVIP

摘要 摘要 万方数据 万方数据 万方数据 万方数据 摘要 JTAG(Joint Test Action Group 联合测试行动小组)技术是可测性设计技术中边 界扫描技术的一种。JTAG 边界扫描分为两种，一种用来检测芯片的电气特性；一 种用在芯片调试阶段，通过 JTAG 接口在电路正常工作期间观测或修改电路的行为。 51MX 一款 8 位 CPU 核，大多数 8 位 CPU 核都没有像 ARM 核一样，带有调 试接口，没有办法在线调试。本设计正是基于这种考虑，在 8 位 CPU 核上添加了 JTAG 接口。51MX 作为 SOC 芯片的 CPU 核，采用复杂指令集，指令和数据长度 都是 8 位，支持标准 51 的所有指令。 FPGA 验证是在 FPGA 开发板上模拟代码的实际工作环境，加上时序，面积等 约束，对代码进行功能仿真验证。所以，进行 FPGA 验证之前，要在原 RTL 代码 上添加 FPGA 仿真需要的代码，之后再用软件仿真，软件仿真通过后，下载到 FPGA 开发板中仿真验证。 本文通过对 IEEE1149.1 协议，51MX CPU 核的深入研究，结合在线调试接口 的应用，设计了一款可以在 51MX 正常工作的情况下，对它的 RAM，ROM 进行 访问，设置程序断点，控制程序单步执行的 JTAG 接口。本设计进行了 RTL 代码 设计，功能仿真，DC 综合以及 FPGA 功能验证。 关键词：JTAG IEEE1149.1 51 FPGA CPU 核 芯片测试 Abst Abstract 万方数据 万方数据 万方数据 万方数据 Abstract JTAG (Joint Test Action Group) is an international standard protocol of testing integrated circuits (IEEE 1149.1). According to its usage, the JTAG interface includes two categories, one is for testing chip’s electrical characteristics, it can test whether the chip has problems and the other one is for debugging, we can observe or modify actions of the circuit during its normal working conditions through JTAG interface. 51MX is an 8 bits CPU core, a large number of 8 bits CPU cores can’t debug on line because of not having JTAG interface. Based on this consideration, my design adds a JTAG interface to 51MX core. As CPU core of the SOC chip, 51MX uses complex instruction set. Its instruction and data are both 8 bits and it supports all the instructions of standard 51 CPU core. FPGA verification verifies RTL code through building actual working environment on FPGA board and adding constraints of timing and area. So we must add code for FPGA verification and simulate all RTL code through simulation software. All above that we can download RTL code to FPGA board. Based on IEEE 1149.1, deepped researching of 51MX CPU and studied some of the applications of the online debug interfaces,this paper designed a JTAG interface that can access 51MX’s RAM, ROM, set breakpoints and execute programs step