通用处理器高带宽访存流水线的研究.docVIP

通用处理器的高带宽访存流水线研究 张浩 范东睿 林伟 钱学海 龙国平 (中国科学院计算技术研究所 北京 100080) 摘要：存储器访问速度的发展远远跟不上处理器运算速度的发展，日益严峻的访存速度问题严重制约了处理器速度的进一步发展。降低load-to-use延迟是提高处理器访存性能的关键，在其他条件确定的情况下，增加访存通路的带宽是降低load-to-use延迟的最有效途径，但增加带宽意味着增加访存通路的硬件逻辑复杂度，势必会增加访存通路的功耗。本文的工作立足于分析程序固有的访存特性，探索高带宽访存流水线的设计和优化空间，分析程序访存行为的规律性，并根据这些规律性给出高带宽访存流水线的低复杂度、低延迟、低功耗解决方案。本文的工作大大简化了高带宽访存流水线的设计，降低了关键路径的时延和功耗，被用于指导Godsonx处理器的访存设计。在处理器整体面积增加1.7%的情况下，将访存流水线的带宽提高了一倍，处理器的整体性能平均提高了8.6%。 关键字：高带宽、访存流水、高速缓存、TLB High-Bandwidth Memory Accessing Pipeline of General Purpose Processor Zhang Hao, Fan Dongrui, Lin Wei, Qian Xuehai, Long Guoping (Institute of Computing Technology, Chinese Academy of Sciences，Beijing, 100080) [Abstract]: There is a near-exponential increase in processor speed and memory capacity. However, memory latencies have not improved as dramatically, and access times are increasingly limiting system performance. Low load-to-use latency is a key to approach high memory performance, and increasing the bandwidth of memory pipeline always works. But high bandwidth brings more complexity and needs more power. Our work is based on the analysis of the applications, and we intend to find the head room of the performance of the memory pipeline. We find some useful characters of memory operations and we give an optimized design of high bandwidth memory pipeline, which has low complexity, low latency and low power. Our decisions are used to instruct the design Godsonx processor, although the bandwidth of memory access is doubled and the performance is increased by 8.6%, the extra area is only 1.7% of the original design. [Key Words]:High Bandwidth, Memory Pipeline, Cache, TLB 引言 根据摩尔定律，微处理器的速度每十年增长十倍以上，而常用存储器(DRAM)的访存时间却只是缩短到原来的一半。因此，相对于处理器 来说，访存延迟以每十年5倍的速度增长。从1986年到2000年，处理器速度的年增长率为55%，而存储器速度的年增长率仅为10%，按照这种速度推算可知，处理器与存储器以及通信性能上的差距不断增加，造成了系统结构的失衡，形成了阻碍性能提升的内存墙 ADDIN REFMGR.CITE RefmanCiteAuthorSaulsbury/AuthorYear1996/YearRecNum139/RecNumIDTextMissing the memory wall: the case for processor/memory integration/IDTextMDL Ref_Type=