一种新型全集成CMOS低噪声放大器优化设计方法.PDFVIP

第5卷 第1期 2010 年 1 月 中国科技论文在线 Sciencepaper Online 47 一种新型全集成 CMOS 低噪声放大器优化设计方法 黄晓华，王先锋，陈抗生，周金芳 （浙江大学信息与电子工程学系电子信息技术与系统研究所，杭州 310027 ） 摘 要：提出一种以几何规划作为全局搜索算法的全集成低噪声放大器优化方法。在优化过程中，将功耗、输入匹配、 器件尺寸等性能参数表示为约束条件，将片上电感寄生电阻噪声和晶体管噪声表示为优化目标，从而将复杂的全集成 LNA优化问题转化为一个能够进行高效求解的几何规划问题。版图后仿真结果表明， 2.4 GHz工作频率下，低噪放 的功耗为4.8 mW ，正向增益S21 可达 17.4 dB，反射参数S11、S22 均小于-20 dB ，三阶互调点IIP3 为-4.2 dBm ，噪声系数 NF仅为 2.0 dB。 关键词：全集成；CMOS低噪声放大器；输入匹配；功耗约束；噪声优化 中图分类号：TN722.3 文献标志码：A 文章编号：1673－7180(2010)01 －0047 －5 A novel design optimization method of fully integrated CMOS low noise amplifier Huang Xiaohua ，Wang Xianfeng ，Chen Kangshen ，Zhou Jinfang (Research Institute of Electronic Information Technology and System, Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310027, China) Abstract: A geometric programming (GP)-based global optimization method of fully integrated CMOS low noise amplifier (LNA) is presented. By setting the circuit components and performance specifications of LNA as design constraints, transistor noise and parasitic resistance noise in the integrated gate inductor as optimization objective, the complicated design problem was formulated as a geometric programming problem. The results of the post-layout simulation showed that the 2.4 GHz LNA, based on CMOS technology, consumed a low DC power of 4.8 mW, noise figure of 2.0 dB, power gain S21 of 17.4 dB, S11, S22 below -20 dB, and input third-order intermodulation product of -4.2 dBm. Key words: fully integrated ；CMOS low noise amplifier ；input matching ；power dissipation constrained ；noise optimization 射频接收机前端的第一个有源电路，它的噪声系数、功 0 引 言