USB210设备控制器IP核VerilogHDL设计.PDFVIP

34 () Vol.3 o. 4 2003 JOUR AL OF A JI G ORMAL U IVERSITY(E GI EERI G A D TECH OLOGY) 2003 USB 210 设备控制器IP 核的Verilog HDL 设计 周芳, 吴宁 ( , 210016, ) [ ] USB 210 IP . UTMI . Xilinx ISE , USB 210 IP Verilog HDL . [ ] USB, IP , VerilogHDL [ ]T 402, [ ]B, [ ] 1672- 1292- (2003)04- 0066- 05 0 引言 USBPC , .USB , USB . , USB . USB .USB :MCU ; USB , USB ,(MCU) USB . . IP(Intellectual Property) .USB IP , IP IC , . IP 3 , / (soft IP core) 0/ (firm IP core) 0/ (hard IP core) 03 . ( ) . USB Control IP , Verilog HDL , , . 1 控制器结构原理 USB 210 USB , USB . [ 1] USB 210 , USB RZI ,,RAM ; ( RAM ) , RZI USB . USB 210 , :UTMI(USBTransceiver Macrocell Interface) UTMI PL(Protocol Layer) . 1. ,UTMI USB 210 , RZI / .,, . : 2003- 09- 09. : , ,1979- , , . : , ,1956- , , , . ) 66 ) ,:USB 210 IP Verilog HDL UTMI Agere Systems USS2x1WA . 1 USB 2. 0 2 控制器与外部芯片的接口 3:(SSRAM) ; ;UTMI . 15 SRAM, 2 @ 16bit= 64 kB. (SSRAM- WE SSRAM- RD) 16SSRAM- DATA 15SRAM- ADDR. 16 DATA16 ADDR DMA (DMA REQ DMA ACK) . 16 15 addr[ 14:0] - - SSRAM , 64kB RAM.16SSRAM USB ,addr[ 15],. [2] UTMI UTMI .UTMI :USB LI ESTATE [ 1:0]UTMI (TxValidTxReady ) (RxActiveRxValidRxError ) 8 60MHz .USB 210 , 480Mb/ S,UTMI 8,60MHz . 3 控制器设计 311 UTMI UTMI USB . Tx FIFO Tx Bus In- terface ;Rx FIFO Rx Bus Interface UMTI USB 8 ; ISE USB , ;S E USB (480Mb/ s) ( 12Mb/ s) . [3] USS2x1WA LI ESTATE[ 1:0] USB ,LI ESTATE[ 1:0]/ 000 ,USB SE0; / 010 J ;/ 100 K ;/ 110SE1.ISE [ 1] USB .