数字逻辑第五章..ppt

三进程描述状态机 ARCHITECTURE state_machine OF store_controller IS TYPE state_type IS (idle,decision,read,write); SIGNAL present_state,next_state : state_type; BEGIN nextstate_logic:PROCESS (present_state,ready,read_write) BEGIN CASE present_state IS WHEN idle = IF (ready =1) THEN next_state = decision; ELSE next_state = idle; END IF; WHEN decision = IF (read_write =1) THEN next_state = read; ELSE next_state = write; END IF; WHEN read = IF (ready =1) THEN next_state = idle; ELSE next_state = read; END IF; WHEN write = IF (ready =1) THEN next_state = idle; ELSE next_state = write; END IF; END CASE; END PROCESS; state_register:PROCESS (clk) BEGIN IF (clkevent AND clk =1) THEN present_state = next_state; END IF; END PROCESS; output_logic:PROCESS (present_state) BEGIN CASE present_state IS WHEN idle = we = 0; re = 0; WHEN decision = we = 0; re = 0; WHEN read = we = 0; re = 1; WHEN write = we = 1; re = 0; END CASE; END PROCESS; END state_machine; LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY store_controller IS PORT (ready : IN std_logic; clk : IN std_logic; read_write : IN std_logic; we,re : OUT std_logic); END store_controller; 三进程状态机 次态逻辑 状态寄存器 输出逻辑 P1