DDS波形发生器VHDL源码.doc

--DDS波形发生器 (Synplify pro 编译通过)--输出频率 Fout = Fclk*2^M/2^N--分辨率 Fclk/2^N--最大输出频率 Fout = Fclk*50%(理论值,抽样定理) --版本1.0??? 2004/9/29?? by JJJ library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity DDS is?generic(ACCWidth : Integer := 16);?????--相位累加器的长度2^N (2^ACCWidth)?port (?? ?CLK:? in std_logic;?????????--系统时钟 FClk?STEP: in std_logic_vector(ACCWidth-1 downto 0);??--步进,即相位累加器的累加增量,控制输出频率 2^M 频率控制字?CHOICE:? in std_logic_vector(1 downto 0);???--波形选择信号? 00:正弦;? 01:三角波;? 10:方波;? 11:不输出(恒为低电平)--?DAOUT : out std_logic_vector(7 downto 0);???--8位DA输出模拟信号,直通方式,如需时钟控制则要修改?DAOUTX: out std_logic_vector(7 downto 0);?DAOUTY: out std_logic_vector(7 downto 0)?);end; architecture DDS of DDS issignal ACC:std_logic_vector(ACCWidth-1 downto 0):=(others =0);signal DAOUT:std_logic_vector(7 downto 0); begin?process(CLK,STEP)?begin????if(CLKevent and CLK=1) then???ACC=ACC+STEP;??end if;?end process; ?process(CHOICE,ACC)?begin??case CHOICE is???when 00=?? --正弦????case ACC(ACCWidth-1 downto ACCWidth-8) is??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DAOUT =??????????????????? when= DA