基于CJTAG电路系统互连信号完整性测试生成的设计-检测技术与自动化装置专业论文.docxVIP

摘 要 摘 要 随着集成电路制造工艺的不断进步、工作频率的不断提高，片上系统内核间的串 扰测试问题已不容轻视，同时系统设计从之前的简单电路板向复杂多芯片片上电路系 统架构的发展，对测试和调试接口提出了更高要求。 本文通过对信号完整性的串扰机理和故障模型理论的分析，提出基于 IEEE1149.7 标准信号完整性框架的设计。首先，对 IEEE 1149.7 标准结构和规范进行分析。然后， 利用 HT（Half Transition）模型的基本思想，设计并实现基于 CJTAG 的信号完整性 （Signal Integrity，SI）测试系统架构。其中，主要工作包括 CJTAG 结构设计与验证， HT 测试种子的生成，以及对数字边界扫描单元、矢量生成型边界扫描单元（PGBSC）、 可观测的信号完整性测试单元（OBSC）以及指令寄存器的设计。本文主要设计思路： 对 CJTAG 系统模块进行设计，并在兼容 IEEE1149.7 的基础上增加了两条 SI 测试指 令，从而实现基于 CJTAG 信号完整性的测试。 本文计构建基于 IEEE1149.7 协议的高速互连信号完整性测试系统，在 Modelsim 软件环境下进行了仿真并对系统进行功能验证。仿真结果表明各模块均能够实现其设 计功能。本文研究的内容不仅为高速信号互连系统的信号完整性测试提供了一种新的 方法，还对 IEEE1149.7 标准规范在边界扫描系统中的研究与设计具有重要的参考价 值。 关键词：边界扫描；CJTAG；HT 模型；信号完整性 I II II Abstract Abstract With the development of integrated circuit manufacturing technology and elevation of working frequency, crosstalk testing problems among cores of system on chip cannot be ignored. Meanwhile, system design has been developed from previous simple circuit board to acomplex multi-core circuit architecture for system on chip, which presents more requirements for testing and debuging interface. Through the analysis of signal integrity crosstalk mechanisms and failure models, the design of signal integrity framework is presented based on IEEE1149.7 Standard. First, the structure and standard of the IEEE 1149.7 Standard are analyzed. Then, applying the basic idea of the HT（Half Transition） model, the signal integrity test system architecture based on CJTAG is designed and implemented. The main work includes the design and verification of the CJTAG structure, the generation of HT test seeds, and the design of digital boundary scan cell, vector generation boundary scan cell（PGBSC）, observable signal integrity test cell （OBSC）, instruction register. The paper’s main design method as following，the CJTAG system module is designed, and two SI directives are defined in compatible with IEEE1149.7 Standard, then the signal integrity test based on CJTAG is realized. The high-speed interconne