指令级并行性及动态扩展.pptVIP

* * * * * * * Instruction-Level Parallelism and Its Dynamic Exploitation * 3.3.5 Pipelining Control Hazards Taxonomy of Hazards Structural hazards These are conflicts over hardware resources. Data hazards Instruction depends on result of prior computation which is not ready (computed or stored) yet OK, we did these, Double Bump, Forwarding path, software scheduling, otherwise have to stall Control hazards branch condition and the branch PC are not available in time to fetch an instruction on the next clock * The Control hazard 一、Cause branch condition and the branch PC are not available in time to fetch an instruction on the next clock The next PC takes time to compute For conditional branches, the branch direction takes time to compute. Control hazards can cause a greater and greater performance loss for MIPS pipeline than do data hazards. * Example: Branches * Branches of Basic Pipelined Datapath * 二、The Penalty of Control hazard b=3 * 三、Dealing with the control hazard Four simple solutions Freeze or flush the pipeline Penalty is fixed. Can not be reduced by software. Predict-not-taken (Predict-untaken) Treat every branch as not taken Predict-taken Treat every branch as taken Delayed branch Note: Fixed hardware Compile time scheme using knowledge of hardware scheme and of branch behavior * (1)Freeze or flush the pipeline * (2)Predict not-taken Hardware: Treat every branch as not taken (or as the formal instruction) When branch is not taken, the fetched instruction just continues to flow on. No stall at all. If the branch is taken, then restart the fetch at the branch target, which cause 3 stall.(should turn the fetched instruction into a no-op) Compiler: Can improve the performance by coding the most frequent case in the untaken path. * (3)Predict –taken Most branches(60%) are taken, so we should make the taken branch more faster. Why not try assuming the branch always taken? Hardware Treat every branch as taken (evidence: more than 60% branches are ta