AT25F1024AN-10SU-27;中文规格书,Datasheet资料.pdf

Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) – Datasheet Describes Mode 0 Operation • 33 MHz Clock Rate • Byte Mode and 256-byte Page Mode for Program Operations • Sector Architecture: – Four Sectors with 32K Bytes Each (1M) – 128 Pages per Sector • Product Identification Mode 1Mbit High • Low-voltage Operation Speed SPI – 2.7 (VCC = 2.7V to 3.6V) • Sector Write Protection Serial Flash • Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection Memory • Self-timed Program Cycle (20 µs/Byte Typical) • Self-timed Sector Erase Cycle (1 second/Sector Typical) 1M (131,072 x 8) • Single Cycle Reprogramming (Erase and Program) for Status Register • High Reliability – Endurance: 10,000 Write Cycles Typical AT25F1024A – Data Retention: 20 Years • Lead-free/Halogen-free Devices • 8-lead JEDEC SOIC and 8-lead SAP Packages Description The AT25F1024A provides 1,048,576 bits of serial reprogrammable Flash memory organized as 131,072 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25F1024A is available in a space-saving 8-lead JEDEC SOIC and 8-lead SAP packages. The AT25F1024A is enabled through the Chip Select pin (CS) and accessed via a 3- wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are co